Approximate computing can be explored for applications where controlled computational errors may be acceptable in exchange for improvements in hardware metrics.
The Approximate Computing in VLSI Design project introduces approximate arithmetic and energy-efficient hardware concepts.
An Approximate Adder for Image Processing project applies approximate arithmetic to image-processing workloads.
Reliable communication systems depend on error-correction algorithms and efficient hardware architectures.
The LDPC Decoder FPGA project explores hardware implementation of Low-Density Parity-Check decoding.
The Turbo Decoder FPGA project focuses on hardware implementation of Turbo decoding algorithms.
The Viterbi Decoder FPGA project demonstrates hardware implementation of the Viterbi algorithm for decoding applications.
Hardware security is increasingly important in processors, IoT devices, smart cards, communication systems, and embedded platforms.
The AES 128 Encryption Verilog project provides practical experience with hardware implementation of AES-128 encryption.
The AES 256 Pipeline Project project explores pipelined AES-256 hardware architecture.
The True Random Number Generator FPGA project investigates FPGA-based random-number generation for security-related applications.
The Hardware Trojan Detection project focuses on hardware security and detection of malicious modifications in integrated circuits.
The Secure Digital Voting System project combines digital logic, security concepts, and system-level hardware design.
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